output timing improvement

I/O timing is a completely different beast then internal timing, and will not easily run at 300MHz(you will most likely have to do source synchronous, where the clock and data are routed together.) But since this is not the real I/O in your design, just ignore it. Don't add a set_output_delay constraint to something that isn't going to be a real I/O.

(And if you do want to improve the clock network delay, use a PLL. THe delay is still there, but the PLL creates a clock that compensates(or basically shifts back in time) the clock it is sending. But again, don't do I/O constraints if it's not a real I/O)

And yes, it can do 300MHz, but it is by no means trivial to do.