output Signal is not constant

I liked the detail in the ripple clocks posts. I read: Don't use them; stay in one clock domain. I used to think there were a handful of reasons to use ripple clocks, but now I only see one reason to use a Flip-Flop derived clock - because the frequency is lower than the minimum output of a PLL. (& tell Quartus to give it a clock buffer. ) One of the guys I work with goes farther and routes this flavor of clock out an output pin and back in a clock input pin. You can put a test pad on it, and it is super clear that it is a clock domain.