-- basic calculation example
-- rewritten 9/14 as a code example, not simulated
-- OUTPUT1 resets with NSL, and increments or decrements based on MSBINV
-- for 14 ticks and starts over.
-- divide the input clock by 6 for SCL
-- start/end indication with NSL
-- keyword fixup indicates possible need for changes

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--use work.mem.all;


entity single is
  port(CLK      : in    bit;
       MSBINV   : in    std_logic;
       DOUT     : in    std_logic;      -- fixup not used
       OUTPUT1  : buffer std_logic_vector(12 downto 1);
       SCL      : buffer std_logic;
       NSL      : out std_logic);

End Entity single;

Architecture single_calc of single is
  
  signal counter : std_logic_vector(6 downto 0);
  signal termCnt : BOOLEAN;             -- counter terminal count
  signal NSLnext : BOOLEAN;             -- same clock sync reset of output
  signal SCLcnt : std_logic_vector(1 downto 0);  -- toggle SCL every 3
  
begin

  termCnt <= TRUE when counter = "1010111" else FALSE;
  -- NSL true during counts 87, and 0 -> 3
  NSLnext <= TRUE when (counter = "1010110" or
                        counter = "1010111" or
                        counter = "0000000" or
                        counter = "0000001" or
                        counter = "0000010") else FALSE;
  
  trans:process(CLK)
  begin 
    if(CLK'event and CLK='1') then
      
      -- count 0 to 87 and roll over to 0
      if termCnt then       -- terminal count x57, decimal 87
        counter <= (others => '0');
      else
        counter <= counter + 1;
      end if;

      -- SCL driven low for 0 -> 6, then toggles every 3 clocks to 87
      if counter <= "0000011" or SCLcnt = "10" then
        SCLcnt <= "00";
      else
        SCLcnt <= SCLcnt + 1;
      end if;
      if termCnt then
        SCL <= '0';
      elsif SCLcnt = "10" then
        SCL <= not SCL;
      end if;
      
      -- NSL true during counts 87, and 0 -> 3
      if NSLnext then
        NSL <= '1';
      else
        NSL <= '0';
      end if;
      
    end if;  
  end process trans;


  pros1 : process(CLK)
  begin
    if(CLK'event and CLK ='1')  then
      if NSLnext then
        OUTPUT1 <= x"000";
      else
        if SCL = '0' and SCLcnt = "10" then
          -- next clock period is SCL pos edge
          if MSBINV = '1' then          -- async input not registered fixup
            OUTPUT1 <= OUTPUT1 + 1;
          else
            OUTPUT1 <= OUTPUT1 - 1;
          end if;                       -- MSBINV
        end if;                         -- SCL
      end if;                           -- NSLnext
    end if;                             -- CLK
  end process pros1;
  
end architecture single_calc;