Output Pins stuck at VCC or GND

I run the code in Quartus simulator (using Stratix III target). If it doesn't compile for this target, you need to use a functional simulator (e.g. ModelSim Altera Edition) or understand the problem from analyzing the code.

Personally, I try to have a more simple and "readable" FSM structure for similar purposes, using only one clocked process (a simplified "Moore" design). It helps to see this kind of problems, but can't avoid them completely.