Output Pins stuck at VCC or GND

I reviewed my previous explanation for synthesis failure of the design, and found, that's it not correct. Actually, LOADADR is active for one clock cycle, I didn't consider that STATE is a registered signal. So it's possibly a synthesis bug, as suspected. You should check, if the Stratix III design gives correct behaviour in Quartus timing simulation.

Sorry for causing confusion.

P.S.: Looking at a Quartus simulation, the receiver state apparently never reaches RECV_DATA, so all outputs are non-functional. Seems like Quartus synthesis came to the same result.