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I don't think it's a Quartus bug. Actually the "RESET CONTROL SIGNALS" related action in the asynchronous process defines ambigious logic. You have e.g.
LOADRDR<='0';
--
WHEN RECV_DATA =>
--
NEXTSTATE<=IDLE;
--
LOADRDR<='1';
In other words LOADADR is set for "no time", so the output data are never written to the output port. Similar things happen most likely to the other outputs. I didn't check, how the design result with Stratix III behaves, but it can't be as intended, I fear.
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Hi FvM,
but why behaves the synthesis so differently ?
Kind regards
GPK
Honored Contributor
