Honored Contributor
Honored ContributorHere is complete example.Now just to find the errors,everybody,maybe helpful to all of us.
--receiver entity Library ieee; use ieee.std_logic_1164.all; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity uart_receiver is port(RxD,bclkX8,sysclk,RDRF,RST_B:in std_logic; RDR:out STD_LOGIC_VECTOR(7 downto 0); SETRDRF,WRONG:out std_logic); end uart_receiver; architecture rcvr_behavior of uart_receiver is TYPE STATETYPE IS (IDLE,START_DETECTED,RECV_DATA); SIGNAL STATE,NEXTSTATE:STATETYPE; SIGNAL RSR:STD_LOGIC_VECTOR(7 DOWNTO 0);--RECEIVE SHIFT REGISTER SIGNAL CT1:INTEGER RANGE 0 TO 7;--INDICATES WHEN TO READ THE RXD INPUT SIGNAL CT2:INTEGER RANGE 0 TO 8;--COUNTS NUMBER OF BITS READ SIGNAL INC1,INC2,CLR1,CLR2,SHFTRSR,LOADRDR:STD_LOGIC; SIGNAL BCLKX8_DLAYED,BCLKX8_RISING:STD_LOGIC; BEGIN BCLKX8_RISING<=BCLKX8 AND NOT BCLKX8_DLAYED; --INDICATES THE RISING EDGE OF BITX8 CLOCK RCVR_CONTROL:PROCESS(STATE,RXD,CT1,CT2,BCLKX8_RISING,rdrf) BEGIN --RESET CONTROL SIGNALS INC1<='0';INC2<='0';CLR1<='0';CLR2<='0';SHFTRSR<='0';LOADRDR<='0'; SETRDRF<='0';WRONG<='0'; CASE STATE IS WHEN IDLE=> IF(RXD='0') THEN NEXTSTATE<=START_DETECTED; ELSE NEXTSTATE<=IDLE; END IF; WHEN START_DETECTED=> IF BCLKX8_RISING='0' THEN NEXTSTATE<=START_DETECTED; ELSIF RXD<='1' THEN CLR1<='1';NEXTSTATE<=IDLE; ELSIF CT1=3 THEN CLR1<='1'; NEXTSTATE<=RECV_DATA; ELSE INC1<='1';NEXTSTATE<=START_DETECTED; END IF; WHEN RECV_DATA=> IF BCLKX8_RISING='0' THEN NEXTSTATE<=RECV_DATA; ELSE INC1<='1'; IF CT1/=7 THEN --WAIT FOR 8 CLKCL CYCLES NEXTSTATE<=RECV_DATA; ELSIF CT2/=8 THEN SHFTRSR<='1';INC2<='1';CLR1<='1';--READ NEXT DATA BIT; NEXTSTATE<=RECV_DATA; ELSE NEXTSTATE<=IDLE;setrdrf<='1';CLR1<='1';CLR2<='1'; IF RDRF='1' THEN WRONG<='1'; else LOADRDR<='1'; END IF; END IF; END IF; END CASE; END PROCESS; RCVR_UPDATE:PROCESS(SYSCLK,RST_B) BEGIN IF RST_B='0' THEN STATE<=IDLE;BCLKX8_DLAYED<='0';CT1<=0;CT2<=0; ELSIF SYSCLK'EVENT AND SYSCLK='1'THEN STATE<=NEXTSTATE; IF CLR1='1' THEN CT1<=0; ELSIF INC1='1' THEN CT1<=CT1+1; END IF; IF CLR2='1' THEN CT2<=0; ELSIF INC2='1' THEN CT2<=CT2+1; END IF; IF SHFTRSR='1' THEN RSR<=RXD & RSR(7 DOWNTO 1); END IF; IF LOADRDR='1' THEN --UPDATE SHIFT REG. RDR<=RSR; END IF; BCLKX8_DLAYED<=BCLKX8;--BCLKX8 DELAYED BY 1 SYSCLK END IF; END PROCESS; END RCVR_BEHAVIOR; following are warnings Warning: Output pins are stuck at VCC or GND Warning (13410): Pin "RDR[0]" is stuck at GND Warning (13410): Pin "RDR[1]" is stuck at GND Warning (13410): Pin "RDR[2]" is stuck at GND Warning (13410): Pin "RDR[3]" is stuck at GND Warning (13410): Pin "RDR[4]" is stuck at GND Warning (13410): Pin "RDR[5]" is stuck at GND Warning (13410): Pin "RDR[6]" is stuck at GND Warning (13410): Pin "RDR[7]" is stuck at GND Warning (13410): Pin "SETRDRF" is stuck at GND Warning (13410): Pin "WRONG" is stuck at GND Warning: Design contains 5 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "bclkX8" Warning (15610): No output dependent on input pin "RDRF" Warning (15610): No output dependent on input pin "sysclk" Warning (15610): No output dependent on input pin "RST_B" Warning (15610): No output dependent on input pin "RxD"
