Output pins are stuck...

Hello pancake,

Thanks for the quick response. Yes, I have simulated quite a bit with varing combinations of operands and operand sizes. The results are pretty consistant. I also used the RTL Viewer to verify that Quartus II quit synthesizing after two layers past the operand size.

I wouldn't be surprised if there were bugs in my code but I just haven't been able to find them. I have a fair amount of experience programming in C/C++ and Java but this is my first exposure to an HDL and it has taken some getting used to. I did attach the package code to the original posting but here it is again:

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library ieee;

use ieee.std_logic_1164.all;

--use ieee.std_logic_signed.all;

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package mult_package is

-- constant n: integer := 7;

function "*"(signal multer, multand: std_logic_vector)

return std_logic_vector;

end package mult_package;

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package body mult_package is

function "*"(

signal multer, multand: std_logic_vector)

return std_logic_vector is

type mult_matrix is array (0 to multer'length + multand'length-1)

of std_logic_vector(multer'length + multand'length-1 downto 0);

variable a, b, c: mult_matrix;

variable prod: std_logic_vector(multer'length + multand'length-1 downto 0);

begin

-------- initialize first row in multiplication matrix --------------

if ((multer(0) xor multer(multer'left)) = '1') then

b(0)(b(0)'left downto multand'length) := (others => multand(multand'left));

b(0)(multand'left downto 0) := multand;

else

b(0) := (others => '0');

end if;

a(0) := (others => '0');

c(0) := (others => '0');

prod(0) := b(0)(0);

-------- load multiplicand matrix and generate products -------------

for j in 1 to multer'left loop

if((multer(j) xor multer(multer'left)) = '1') then

a(j)(a(j)'left downto multand'length) := (others => multand(multand'left));

a(j)(multand'left+j downto j) := multand;

else

a(j) := (others => '0');

end if;

for i in j to multand'length+j loop

b(j)(i) := a(j )(i) xor b(j-1)(i) xor c(j-1)(i-1);

c(j)(i) := (a(j )(i) and b(j-1)(i))

or (a(j )(i) and c(j-1)(i-1))

or (b(j-1)(i) and c(j-1)(i-1));

end loop;

prod(j) := b(j)(j);

end loop;

--------------------- final carry propagation -----------------------

for j in multer'length to b'high loop

b(j)(b(j)'high downto j) := b(j-1)(b(j-1)'high downto j) xor c(j-1)(c(j-1)'high-1 downto j-1);

c(j)(c(j)'high downto j) := b(j-1)(b(j-1)'high downto j) and c(j-1)(c(j-1)'high-1 downto j-1);

prod(j) := b(j)(j);

end loop;

--return "00" & prod & "00" & a(n) & "00" & c(n-1) & "00" & b(n) & "00" & c(n);

return prod;

end function "*";

end package body mult_package;

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There are a couple lines of debug code included and commented out.

The sythesizer seems to quit after two iterations of the second loop.

Thanks again for your reply and your interst.

Dave