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I think that it should be like
create_generated_clock clk_at_ext_device -offset min_ExternalClockDelay ...
set_output_delay -clock clk_at_ext_device -max [expr tSUext + MaxDataExtDelay] ...
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It is the same thing. Once again, you must think in terms of the relation between clock and data. The relation between clock and data depends here on the external delay skew.
So it is the same if you include the skew at the offset parameter, or at the output constraint, or half on each one of them. The absolute numbers at the clock generation and at the output constraints are not significant. Only the relation between both of them is.
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create_generated_clock ... (no offset parameter)
set_output_delay -max [expr tSUext + MaxExtDelaySkew - Min_Clock_PCB_delay] ...
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No, this is wrong. If you don't offset the clock at the clock generation, then you can't offset the constraint. The only thing you add to the external tSU is the worst external delay skew (skew only, no absolute delay).
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We need a PLL to create clk and ref_clk. The phase shift between them is not known in advance. Before we set input/output constraints, we need to create clk and ref_clk or configure the PLL.
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Yes, that is correct. You can't know the optimum PLL phase shift before you do a timing analysis. But this is not trial and error. It is just a matter of doing timing analysis only once.
You do the following. You first make a compilation and timing analysis without any PLL phase shift. The TimeQuest report would tell you then, what is your maximum and mimum clock to output at the FPGA. It would also tell you the I/O setup and hold slack. You use these reports to compute your ideal PLL phase shift.
For this method to work you must use Fast I/O registers for your I/O ports. Otherwise the timing might change on each compilation. Using Fast I/O registers is recommended anyway to reduce skew as much as possible.
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