Output delay with or without clock shift

vjAlter,

I really appreciate your answers/comments. It is nearly to the point where we reach the conclusion.

The following is just minor things.

"create_generated_clock -offset ExternalClockDelay ...

set_output_delay -max [expr tSUext + MaxDataExtDelay + clockExtDelaySkew] ..."

I think that it should be like

create_generated_clock clk_at_ext_device -offset min_ExternalClockDelay ...

set_output_delay -clock clk_at_ext_device -max [expr tSUext + MaxDataExtDelay] ...

For

"create_generated_clock ... (no offset parameter)

set_output_delay -max [expr tSUext + MaxExtDelaySkew] ..."

I think that it should be

create_generated_clock ... (no offset parameter)

set_output_delay -max [expr tSUext + MaxExtDelaySkew - Min_Clock_PCB_delay] ...

The TimeQuest uses 2 different clocks, one for the source register (output register) - I call it clk, and the other for the external device such as SSRAM - I call it ref_clk, for timing analysis. We need a PLL to create clk and ref_clk. The phase shift between them is not known in advance. Before we set input/output constraints, we need to create clk and ref_clk or configure the PLL. When we create ref_clk or configure the PLL, we only can provide estimated values for the phase shift. Is my point clear?

Many thanks