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For example, the ref_clk_pin and ref_clk_pin2 could the clock at the clock output pin of the FPGA device and the clock at the clock input pin of the external device, recpectively. They could be two clocks in two different places. When you set your constraints, you only use one of them.
What I meant is that if you move the reference clock to a different point when you set your constraints, those three things have to be considered together.
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If you change the reference clock from the FPGA pin to the target device pin, you also change the output constraints. But this doesn't affect TimeQuest, it is just a different conventional point of view. In both cases TimeQuest would compute the same timing, you would get the same slack, and the ideal PLL phase shift would be identical.
Let's say that you consider the reference clock at the target device. You then add the offset parameter at the clock generation. This moves the clock timing from the FPGA to the target device. But then you also must move the data output from the FPGA pins to the target. You do this by adding the external delay to the output constraints:
create_generated_clock -offset ExternalClockDelay ...
set_output_delay -max [expr tSUext + MaxDataExtDelay + clockExtDelaySkew] ...
If you consider the reference clock at the FPGA pin, as Rysc recommends, you don't use the offset parameter. But you don't add the external delay to the output constraint either, only the external delay
skew:
create_generated_clock ... (no offset parameter)
set_output_delay -max [expr tSUext + MaxExtDelaySkew] ...
Both constraints are technically the same for TimeQuest. It is just two different ways to specify the same thing. What always matters is the relation between clock and data, this gives you the setup and hold slack. And in both cases the relation between clock and data is the same.
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