Output delay with or without clock shift

"What do you mean by ref_clk_pin and ref_clk_pin2? Why do you have two different output clocks? Are you using a differential clock, or you still didn't define the board pinout? Or you mean two different generated clocks, at the same pin but with different generated clock parameters?"

For example, the ref_clk_pin and ref_clk_pin2 could the clock at the clock output pin of the FPGA device and the clock at the clock input pin of the external device, recpectively. They could be two clocks in two different places. When you set your constraints, you only use one of them.

What I meant is that if you move the reference clock to a different point when you set your constraints, those three things have to be considered together.