Output delay with or without clock shift

vjAlter,

Thank you very much indeed.

set_output_delay -add_delay -max -clock [get_clocks {ref_clk_pin}] output_max_delay [get_ports {q[0]}] [1]

In the above equation, it seems that the clock at ref_clk_pin is irrelevant to the output_max_delay. However, they are not independent. Output_max_delay is caluculted as max_data_delay + tSUext –min_clock_delay, where min_clock_delay is the delay from ref_clk_pin to the clock pin of the external device. If you change the equation as follows for example,

set_output_delay -add_delay -max -clock [get_clocks {ref_clk_pin2}] output_max_delay2 [get_ports {q[0]}] [2]

then output_max_delay2 = max_data_delay + tSUext – min_clock_delay2, where min_clock_delay2 is the delay from ref_clk_pin2 to the clock pin of the external device.

What I said earlier is that when we configure a PLL, we have to consider the delay from the output of the PLL to ref_clk_pin or to ref_clk_pin2. We can't simply put a value of output_max_delay there without considering the above 3 factors. As a result, when we change from equation [1] to equation [2], we have to re-calculate the output_max_delay value and have to adjust the PLL phase shift to generate ref_clk_pin2 accordingly. How to adjust the phase shift has to be through trial and error.