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Suppose that clk_pin is a clock generated by a PLL. How do you know that the delay from the PLL output to the clock output pin in adavance?
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you don't know, but TimeQuest does know. TimeQuest knows both the PLL phase shift and compensation, and the delay from the PLL to the output pin.
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If the clock offset is calculated, the output max/min delay can be defined with respect to the offseted clock, output max delay should be defined as max data delay + tSUext. Then, set_output_delay -add_delay -max -clock offset_clock_pin (2.100 + clock offset) [get_ports {q[0]}].
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You are again mixing up internal with external clock delays. The internal delays are known by TimeQuest, you don't need to compute them or specify them.
The external delay (which is what is specified as clock offset in those examples you have seen) is, of course, not known by TimeQuest. But the external delay is not relevant for outputs. It doesn't matter how much time it takes from the clock pin to the target device, it only matters the maximum external skew between clock and data.
So you can do as Rysc suggests, forget about the offset and external delay altogether, and just add the maximum skew to the device Tsu and Th.
Or, if you want, you can use offset as in those examples. But again, this is only the external delay, not the internal one. If you use the offset in the clock generation, you must add it also in the output constraints.
You don't gain anything by using the offset for outputs. The only reason to use it is for the input constraints, because the external delay does matter for inputs.
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