Output delay with or without clock shift

Thanks, vjAlter and Rysc.

The output max/min delay is defined with respect to the clock at the output clock pin of FPGA. For example, output max delay = max data delay + tSUext - min clock delay (PCB clock skew).

set_output_delay -add_delay -max -clock [get_clocks {clk_pin}] 2.100 [get_ports {q[0]}]

Suppose that clk_pin is a clock generated by a PLL. How do you know that the delay from the PLL output to the clock output pin in adavance?

If the clock offset is calculated, the output max/min delay can be defined with respect to the offseted clock, output max delay should be defined as max data delay + tSUext. Then, set_output_delay -add_delay -max -clock offset_clock_pin (2.100 + clock offset) [get_ports {q[0]}].