Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Output delay with or without clock shift

Here is a very simple example as attached. The output delays are set as follows. set_output_delay -add_delay -max -clock [get_clocks {clk_pin}] 2.100 [get_ports {q[0]}] set_output_delay -ad...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Yes, the output data and clock are created from the same input clock in the FPGA, so TimeQuest knows the max and min relationship between the two. Your generated clock only needs to say there is a clock going out this port so it can be referenced by your set_output_delay constraint. So no offset should be used.