Output delay with or without clock shift

Seems you are mixing up clock offset with clock shift and delay.

Clock offset is normally the trace board delay from the output clock pin to the target device. This is typically in the order of 0.5 nanoseconds as used in many examples.

Clock shift is the phase shift between two clocks. If you are generating the clock with an internal PLL, TimeQuest already knows the PLL shift. Internal clock delays are also known by TimeQuest.

You get the same result with or without clock offset on the clock generation. You just must adjust the output delay constraint accordingly. The samples you mention use the clock offset, and then the offset is also added in the output constraint.