Out of memory during compilation

We've had the same problem - the only solutions:

1. Keep trying again. close all other applications and leave the PC alone. Sometimes it works some times it doesnt.

2. Find a computer with a 64bit OS and >3GB Ram.

The minimum spec for some of the larger devices is 3GB.

thanks for ur reply. Then i am thinking of buying a new pc d. If that is the case, what is the spec of pc suggested?

Besides, is QII support 64 bit Windows 7? I have checked with the altera website stated Qii doesn't support windows 7. However, i have a fren using 64 bit windows 7 to run 64bit QII. He uses the command shell instead of GUI, never face any problem. What do you think?

--- Quote Start ---

thanks for ur reply. Then i am thinking of buying a new pc d. If that is the case, what is the spec of pc suggested?

Besides, is QII support 64 bit Windows 7? I have checked with the altera website stated Qii doesn't support windows 7. However, i have a fren using 64 bit windows 7 to run 64bit QII. He uses the command shell instead of GUI, never face any problem. What do you think?

--- Quote End ---

Hi,

I tried your design with a 8Gbyte 64bit Vista PC. It also fails. I had a brief look into your code. What you are trying is to implement a memory ( reg [7:0] q [299:0]), but due to your loop statements Quartus has to implement the memory as registers with a lot of multiplexers. I believe this is to complex. It doesn't help that you use only some bits as outputs, because the optimization takes place after the synthesis step.

Kind regards

GPK

--- Quote Start ---

Even though the output of q0 and q299 are taken away, the Qii synthesis the design wrongly.

--- Quote End ---

Hi,

you are still running out of memory ?

Kind regards

GPK

nope.

if try to use it, it will run out of memory again. Seems like i cant use this method

--- Quote Start ---

nope.

if try to use it, it will run out of memory again. Seems like i cant use this method

--- Quote End ---

Hi,

maybe this is what you try to achieve ?

module double_loop_input_as_condition (clk, d, q0, q299, count);

input clk;

input [7:0] d;

output [7:0] q0 , q299;

output reg [8:0] count;

reg [7:0] q [300:0];

reg [8:0] offset;

integer i;

integer j;

integer num_reg;

//simulation shows that it cant assign the integer to a register

always @ (posedge clk)

begin

num_reg = 100;

q[0] <= d;

count <= count +1;

for (i=0; i<=2; i= i+1)

begin

for (j=1; j <=num_reg; j= j+1)

q[j+(i*num_reg)] <= q[j-1+(i*num_reg)]; end

end

assign q0 = q[0];

assign q299 = q[299];

endmodule

pletz,

thanks for your effort. My intention is to control number of shifting of sets of shift register. The number of shifting is a input type

From ur code, number of shifting is fixed d. It is contradict with my intention.

Anyway thanks.

--- Quote Start ---

pletz,

thanks for your effort. My intention is to control number of shifting of sets of shift register. The number of shifting is a input type

From ur code, number of shifting is fixed d. It is contradict with my intention.

Anyway thanks.

--- Quote End ---

Hi,

you have to keep in mind that your code is converted to hardware by the synthesis tool.

With num_reg as input which number of inputs should the synthesis tool use ?

Kind regards

GPK