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Altera_Forum's avatar
Altera_Forum
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12 years ago

Optimizing a set of registers

I am working on optimizing a processor I made (size-wise) and I noticed that the register set is quite large (about 1000 LEs) I looked into the sysnthesized logic using the RTL viewer and it looked very messy (I am trying to upload an image of it) with over 100 multiplexers and lots of unnecessary signals.

I am wondering how I can make it so the design is simpler (i.e. the logic is composed of the register, two multiplexers [for reads], and one de-multiplexer [for writing]).

The VHDL code I used is listed here: 


entity default_registers is
port (
      
	   input : in std_logic_vector(31 downto 0);
		
		register_to_write : in std_logic_vector (4 downto 0);
		write_to_register : in std_logic;
		register_to_read_a : in std_logic_vector (4 downto 0);
		register_to_read_b : in std_logic_vector (4 downto 0);	
		clk : in std_logic;		
		clear: in std_logic;
		
		output0 : out std_logic_vector(31 downto 0);
		output1 : out std_logic_vector(31 downto 0)
		
     );
end default_registers;
architecture Behavioral of default_registers is
signal register1 : std_logic_vector (31 downto 0);
signal register2 : std_logic_vector (31 downto 0);
signal register3 : std_logic_vector (31 downto 0);
signal register4 : std_logic_vector (31 downto 0);
signal register5 : std_logic_vector (31 downto 0);
signal register6 : std_logic_vector (31 downto 0);
signal register7 : std_logic_vector (31 downto 0);
signal register8 : std_logic_vector (31 downto 0);
signal register9 : std_logic_vector (31 downto 0);
signal register10 : std_logic_vector (31 downto 0);
signal register11 : std_logic_vector (31 downto 0);
signal register12 : std_logic_vector (31 downto 0);
signal register13 : std_logic_vector (31 downto 0);
signal register14 : std_logic_vector (31 downto 0);
signal register15 : std_logic_vector (31 downto 0);
signal register16 : std_logic_vector (31 downto 0);
signal register17 : std_logic_vector (31 downto 0);
signal register18 : std_logic_vector (31 downto 0);
signal register19 : std_logic_vector (31 downto 0);
signal register20 : std_logic_vector (31 downto 0);
signal register21 : std_logic_vector (31 downto 0);
signal register22 : std_logic_vector (31 downto 0);
signal register23 : std_logic_vector (31 downto 0);
signal register24 : std_logic_vector (31 downto 0);
signal register25 : std_logic_vector (31 downto 0);
signal register26 : std_logic_vector (31 downto 0);
signal register27 : std_logic_vector (31 downto 0);
signal register28 : std_logic_vector (31 downto 0);
signal register29 : std_logic_vector (31 downto 0);
signal register30 : std_logic_vector (31 downto 0);
signal register31 : std_logic_vector (31 downto 0);
begin
process(clear, clk, write_to_register)
begin
if clear = '1' then
register1 <= (others => '0');
register2 <= (others => '0');
register3 <= (others => '0');
register4 <= (others => '0');
register5 <= (others => '0');
register6 <= (others => '0');
register7 <= (others => '0');
register8 <= (others => '0');
register9 <= (others => '0');
register10 <= (others => '0');
register11 <= (others => '0');
register12 <= (others => '0');
register13 <= (others => '0');
register14 <= (others => '0');
register15 <= (others => '0');
register16 <= (others => '0');
register17 <= (others => '0');
register18 <= (others => '0');
register19 <= (others => '0');
register20 <= (others => '0');
register21 <= (others => '0');
register22 <= (others => '0');
register23 <= (others => '0');
register24 <= (others => '0');
register25 <= (others => '0');
register26 <= (others => '0');
register27 <= (others => '0');
register28 <= (others => '0');
register29 <= (others => '0');
register30 <= (others => '0');
register31 <= (others => '0');
elsif falling_edge(clk) then 
if write_to_register = '1' then
case register_to_write is
when "00000" =>
-- Do nothing since register0 is always zero
when "00001" =>
register1 <= input;
when "00010" =>
register2 <= input;
when "00011" =>
register3 <= input;
when "00100" =>
register4 <= input;
when "00101" =>
register5 <= input;
when "00110" =>
register6 <= input;
when "00111" =>
register7 <= input;
when "01000" =>
register8 <= input;
when "01001" =>
register9 <= input;
when "01010" =>
register10 <= input;
when "01011" =>
register11 <= input;
when "01100" =>
register12 <= input;
when "01101" =>
register13 <= input;
when "01110" =>
register14 <= input;
when "01111" =>
register15 <= input;
when "10000" =>
register16 <= input;
when "10001" =>
register17 <= input;
when "10010" =>
register18 <= input;
when "10011" =>
register19 <= input;
when "10100" => 
register20 <= input;
when "10101" =>
register21 <= input;
when "10110" =>
register22 <= input;
when "10111" =>
register23 <= input;
when "11000" =>
register24 <= input;
when "11001" =>
register25 <= input;
when "11010" =>
register26 <= input;
when "11011" =>
register27 <= input;
when "11100" =>
register28 <= input;
when "11101" =>
register29 <= input;
when "11110" =>
register30 <= input;
when "11111" =>
register31 <= input;
when others =>
end case;
end if;
end if;
end process;
process (register_to_read_a, register_to_read_b)
begin
case register_to_read_a is
when "00000" =>
output0 <= (others => '0');
when "00001" =>
output0 <= register1;
when "00010" =>
output0 <= register2;
when "00011" =>
output0 <= register3;
when "00100" =>
output0 <= register4;
when "00101" =>
output0 <= register5;
when "00110" =>
output0 <= register6;
when "00111" =>
output0 <= register7;
when "01000" =>
output0 <= register8;
when "01001" =>
output0 <= register9;
when "01010" =>
output0 <= register10;
when "01011" =>
output0 <= register11;
when "01100" =>
output0 <= register12;
when "01101" =>
output0 <= register13;
when "01110" =>
output0 <= register14;
when "01111" =>
output0 <= register15;
when "10000" =>
output0 <= register16;
when "10001" =>
output0 <= register17;
when "10010" =>
output0 <= register18;
when "10011" =>
output0 <= register19;
when "10100" =>
output0 <= register20;
when "10101" =>
output0 <= register21;
when "10110" =>
output0 <= register22;
when "10111" =>
output0 <= register23;
when "11000" =>
output0 <= register24;
when "11001" =>
output0 <= register25;
when "11010" =>
output0 <= register26;
when "11011" =>
output0 <= register27;
when "11100" =>
output0 <= register28;
when "11101" =>
output0 <= register29;
when "11110" =>
output0 <= register30;
when "11111" =>
output0 <= register31;
when others =>
end case;
case register_to_read_b is
when "00000" =>
output1 <= (others => '0');
when "00001" =>
output1 <= register1;
when "00010" =>
output1 <= register2;
when "00011" =>
output1 <= register3;
when "00100" =>
output1 <= register4;
when "00101" =>
output1 <= register5;
when "00110" =>
output1 <= register6;
when "00111" =>
output1 <= register7;
when "01000" =>
output1 <= register8;
when "01001" =>
output1 <= register9;
when "01010" =>
output1 <= register10;
when "01011" =>
output1 <= register11;
when "01100" =>
output1 <= register12;
when "01101" =>
output1 <= register13;
when "01110" =>
output1 <= register14;
when "01111" =>
output1 <= register15;
when "10000" =>
output1 <= register16;
when "10001" =>
output1 <= register17;
when "10010" =>
output1 <= register18;
when "10011" =>
output1 <= register19;
when "10100" =>
output1 <= register20;
when "10101" =>
output1 <= register21;
when "10110" =>
output1 <= register22;
when "10111" =>
output1 <= register23;
when "11000" =>
output1 <= register24;
when "11001" =>
output1 <= register25;
when "11010" =>
output1 <= register26;
when "11011" =>
output1 <= register27;
when "11100" =>
output1 <= register28;
when "11101" =>
output1 <= register29;
when "11110" =>
output1 <= register30;
when "11111" =>
output1 <= register31;
when others =>
end case;  
end process;
end Behavioral;

22 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    you can readily use two rams each with 5 bit address. you write input to both rams(same copy). you then read out to output0 and output1 from ram1,ram2.

    otherwise your logic is ok but I will register the outputs
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    you can readily use two rams each with 5 bit address. you write input to both rams(same copy). you then read out to output0 and output1 from ram1,ram2.

    --- Quote End ---

    Can the ram be implemented directly in the VHDL code in a method that won't require making another file (or component if possible)?

    --- Quote Start ---

    otherwise your logic is ok but I will register the outputs

    --- Quote End ---

    My outputs are registered in a different component that is external of the one that I have posted.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    Can the ram be implemented directly in the VHDL code in a method that won't require making another file (or component if possible)?

    My outputs are registered in a different component that is external of the one that I have posted.

    --- Quote End ---

    yes you can infer ram in vhdl code for either one port or dual port. There are templates from altera and possibly quartus for that.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    One question: Wouldn't using 2 ram blocks take up more space than needed if I was to just use 2 multiplexors, 1 de-multiplexor, and 31 (not 32 as register 0 is always 0) registers?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    One question: Wouldn't using 2 ram blocks take up more space than needed if I was to just use 2 multiplexors, 1 de-multiplexor, and 31 (not 32 as register 0 is always 0) registers?

    --- Quote End ---

    you are using 31 x 32 = 992 registers(flops).

    you are also using a lot of logic.

    This is not wrong if indeed you need access to several registers at same time. But since you access one at a time then a ram can do it.

    two dedicated rams take no logic in the fabric apart from addressing. They are already there in the fpga empty.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    you are using 31 x 32 = 992 registers(flops).

    you are also using a lot of logic.

    This is not wrong if indeed you need access to several registers at same time. But since you access one at a time then a ram can do it.

    two dedicated rams take no logic in the fabric apart from addressing. They are already there in the fpga empty.

    --- Quote End ---

    I am reading two values at once from the regiser file so I assume logic would be the better choice. Is there any way to use my write selector as a selector for a de-multiplexor that connects to the write port of every register. The input to the demultiplexor would be write_to register signal.

    I also don't want to use ram as I am using a large amount of it for my caches.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    Is there any way to use my write selector as a selector for a de-multiplexor that connects to the write port of every register. The input to the demultiplexor would be write_to register signal.

    --- Quote End ---

    I don't quite get it, you are already doing that.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    I don't quite get it, you are already doing that.

    --- Quote End ---

    It doesn't seem to be doing it that way in the RTL viewer though. I will post a pciture when I can to show the issue (tommorow).
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    here (http://i.imgur.com/vhf2qc6.png) is my relatively rubbish picture of a portion of the circuit that I could upload. Please note the large number of muxes that there are. There seem to be too many of them.

    Edit: On a side note, I am wondering how you can have multiple buses go to one output (same width as each bus). I am currently ORing the buses together, but it takes up a large number of LEs.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    If you would get rid of the 'clear' signal you could implement this register bank with a dual port memory.

    You just need to test for address zero and prevent a write to the memory when this address is selected.

    But as long as a your 'clear' signal is required you will end up with 31*32 = 992 registers and two big 32 bit wide 31:1 multiplexers.