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Altera_Forum
Honored Contributor
Honored ContributorOptimisation issues
Hi, is there any way to find out WHY Quartus is optimising away stuff? I know I've almost certainly got something wrong in my VHDL, but I've found that several of my signals/registers are 'missing' o...
Altera_ForumHonored Contributor
Honored ContributorNo, SignalTap would have been fine. It wasn't a 'metastable' type timing problem, it was a me-doing-things-in-the-wrong-order type timing problem :-) So, it would have shown that. I was sending data onto an external CPU's data-bus at totally the wrong time in its clock cycle (200ns too early) so it wasn't seeing it.
(Modelsim is a different issue - I'm struggling with that because I'm using a NIOS II, SDRAM, etc and really don't know what if/how I can simulate that ;-) For simpler components I've managed and it's fine, but in this case it was an interface between the NIOS II and an external CPU which was the problem, so simulating that accurately wasn't going to be trivial for a noob like me... )
