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Altera_Forum's avatar
Altera_Forum
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10 years ago

Optimisation issues

Hi, is there any way to find out WHY Quartus is optimising away stuff? I know I've almost certainly got something wrong in my VHDL, but I've found that several of my signals/registers are 'missing' o...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

BTW - I think I've found why the FPGA isn't working, and it wasn't an optimisation issue, it was a timing one. It'll have to wait until I get home tonight before I can test it out, but the mistake I've found makes sense.

But I'm still not sure if I should have been able to do what I wanted in SignalTap - if I had been, I think I'd have found the problem sooner. I think my confusion with that lead me to wasting time investigating in the wrong places. I think I may need to experiment a bit more to see if I can work out how SignalTap is handling the signal naming.