Optimal ALU

The following SystemVerilog code has been compiled with Quartus Prime 16.0.0, targeting Cyclone V 5CGXFC5C6F27C7. Inputs are synchronous.

module Alu(input logic  operand1, operand2, input logic  control, input logic clock, output logic result);
    always_ff @(posedge clock) begin
        case (control)
            'h0: result <= operand1 + operand2;
            'h1: result <= operand1 - operand2;
            'h2: result <= operand1 & operand2;
            'h3: result <= operand1 | operand2;
        endcase
    end
endmodule

For this ALU, there is a difference of a few MHz for an average frequency of 800MHz between the fastest and the slowest design. However, for a bigger ALU implementing all NIOS II's arithmetic (except multiply and divide) and logical operations, the fastest design I found is clocked at 200MHz while the slowest runs at 150MHz… That's huge, and just by changing operations order!