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Are you targeting an SoC variant of Cyclone V for your kernel design?
The emulator just requires you to target an installed BSP. If you have a BSP for your board installed (which one?), then just try it to see if it works.
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Thank you very much for replying the question :D. I think that you misunderstand my problem. For clarify the thing I will describe the process and the problems.
I am developing over the SOC-FPGA Cyclone V (Cyclone V SoC Development Kit) a OpenCL application which is composed of two application, host and kernel application. The host application will run inside of the SOC part, and the kernel application will run in FPGA part of Cyclone V. I am following the getting started guide of Intel OpenCL SDK for this board, and everything works perfect.
A full compilation could take hours, and this is a important waste of time for a continuously developing. Trying to use wisely the time, now I am following the approach of emulation, which consist in not to do a full compilation, and test the syntax and operation using emulation of the project.
Issues related to this are following:
- Emulation is only linux process, and in this moment I have license for windows Intel OpenCL SDK, so change to linux is not easy at all.
- The guide is not clear for me since it said that the emulation of the kernel will be done on non-SOC FPGA which for me means a FPGA pure, and I just have the Cyclone V board.
- I am understanding that emulation part needs a extra FPGA conected to computer by using PCI express, and on this way, the kernel will be emulated in FPGA and the host application in linux. It is my interpretation of the guide.
I will appreciate if you can clarify all my doubts.
I attach the documentation that I'm using:
https://www.altera.com/en_us/pdfs/literature/hb/opencl-sdk/aocl_c5soc_getting_started.pdf (page 38)
PD: I am thinking in a possible solution for improve the development time which consists in develop the application over my laptop using OpenCL Intel SDK for x86/x64 processor without be worried for hardware accdelration and focus on the correct functionality of the code, and then make a full compilation for cyclone V wasting the time needed and changing the focus to hardware acceleration results. However, extra issues rise, as the Intel OpenCL SDK for x86/x64 processors uses OpenCL version 2.0 and the supported version for the cyclone V is 1.0. I did a question related to a version of SDK with OpenCL 1.0 in Intel forums (
https://software.intel.com/en-us/forums/opencl/topic/740813) for conclude if this approach is possible or not. However if you have a suggestion or know a different approach for development, let me know. I will be deeply thankful.
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