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Altera_Forum's avatar
Altera_Forum
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13 years ago

open and close door

i write these but i'm not sure

LIBRARY IEEE;

USE IEEE.std_logic_1164.all;

USE IEEE.std_logic_unsigned.all;

ENTITY reg1 IS

PORT ( d : in STD_LOGIC;

clk : in STD_LOGIC;

q : out STD_LOGIC);

END reg1;

ARCHITECTURE reg1 OF reg1 IS

SIGNAL a, b : STD_LOGIC;

BEGIN

PROCESS (clk)

BEGIN

IF rising_edge(clk) THEN

a <= d;

b <= a;

q <= b;

END IF;

END PROCESS;

END reg1;

process (reset_n, CLOCK)

begin

if reset_n = '0' then

state <= open_1;

elsif (rising_edge(CLOCK)) then

case state is

open_1 =>

when closed_2=>

end case;

end if;

end process;

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Does it work?

    The first section is doing well registering d input twice into q output but without obvious purpose.

    The process underneath is a mystery. It can't be there.

    What do you actually want the fpga to do with the door?

    If you want simple logic control to open/close door and assuming you have one input called "ctrl" as a short pulse indicating close if open, open if close then:

    PROCESS (clk)

    BEGIN

    IF rising_edge(clk) THEN

    ctrl_d <= ctrl;

    if ctrl /= ctrl_d then -- detect change by user

    toggle <= not toggle;

    end if;

    q <= toggle; -- should settle as either 0 or 1

    END IF;

    END PROCESS;

    to prevent the door being getting stuck in wrong state or bounce back dangerously then you need to define a reset state and debounce the ctrl input.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    OK, here is another example. A prison door(far from all vhdl designers) requires a secret code to unlock. 

    
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
ENTITY door_key IS
PORT ( 
       d : in STD_LOGIC_vector(15 downto 0);
      clk : in STD_LOGIC;
      q : out STD_LOGIC);
END entity;
ARCHITECTURE rtl OF door_key IS
  
BEGIN
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
    if d = x"1234" then
       q <= '1';
    else 
       q <= '0';
END IF;
END PROCESS;
END rtl;

    I am sorry you may have English language difficulty, if you can explain what is the requirement then we may help better.