open and close door

OK, here is another example. A prison door(far from all vhdl designers) requires a secret code to unlock.

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
ENTITY door_key IS
PORT ( 
       d : in STD_LOGIC_vector(15 downto 0);
      clk : in STD_LOGIC;
      q : out STD_LOGIC);
END entity;
ARCHITECTURE rtl OF door_key IS
  
BEGIN
PROCESS (clk)
BEGIN
IF rising_edge(clk) THEN
    if d = x"1234" then
       q <= '1';
    else 
       q <= '0';
END IF;
END PROCESS;
END rtl;