One shot pulse

Hi all,

I am beginner in VHDL. I am doing tutorial for one shot pulse. But, I am little bit confuse. What does 'idle' meaning in this code? and how do I can modify this VHDL code to generate pulse signal? I try to change the VHDL code by modifying the pulse <= '1'; to 0,1,0 in order to make it pulse signal. When I programmed into FPGA board, the light always on. Why does it happens?

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library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity pulse_5clk is

port (clk,reset: in std_logic;--reset=SW17

go,stop: in std_logic;--go = SW0, stop =SW1

pulse: out std_logic);--pulse=LEDR0

end pulse_5clk;

architecture fsm_arch of pulse_5clk is

type fsm_state_type is

(idle,delay1,delay2,delay3,delay4,delay5);

signal state_reg, state_next: fsm_state_type;

begin

--state register

process (clk,reset)

begin

if (reset='1') then

state_reg <=idle;

elsif (clk'event and clk='1') then

state_reg <=state_next;

end if;

end process;

--next-state logic & output logic

process (state_reg,go,stop)

begin

pulse <='0';

case state_reg is

when idle =>

if go = '1' then

state_next <=delay1;

else

state_next <=idle;

end if;

when delay1 =>

if stop = '1' then

state_next <=idle;

else

state_next <=delay2;

end if;

pulse <= '1';

when delay2 =>

if stop = '1' then

state_next <=idle;

else

state_next <=delay3;

end if;

pulse <= '1';

when delay3 =>

if stop = '1' then

state_next <=idle;

else

state_next <=delay4;

end if;

pulse <= '1';

when delay4 =>

if stop = '1' then

state_next <=idle;

else

state_next <=delay5;

end if;

pulse <= '1';

when delay5 =>

state_next <=idle;

pulse <= '1';

end case;

end process;

end fsm_arch;