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What does 'idle' meaning in this code? and how do I can modify this VHDL code to generate pulse signal? I try to change the VHDL code by modifying the pulse <= '1'; to 0,1,0 in order to make it pulse signal. When I programmed into FPGA board, the light always on. Why does it happens?
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idle is the state name same as other state name mentioned in the design like delay1,delay2 etc.You can observe that pulse signal is not assigned any value when state machine is in idle
state.In this case it will hold its previous value which is "1" .So if you assign pulse <= '0' in idle state,led shouldn't glow. You should verify this using Modelsim before trying to test on hardware. One more thing if the clock frequency is very high, then you won't be able to observe the led "on" and "off" state. You need to slow down the clock using counter if clock frequency is very high.
Regards,
Krupesh