Forum Discussion
Is this a Clock Domain Crossing? As you mentioned there are two different clock domain.
You may check out this on how to properly constrain CDC.
https://learning.intel.com/developer/learn/courses/211/clock-domain-crossing-considerations
Regards,
Richard Tan
- MinzhiWang1 year ago
Occasional Contributor
Hi Tan,
It should be of false paths.
BTW, I can't open the course from your above link.
I tried to apply false path constrain in my project. According to above recovery timing violation report from TimeQuest, both lauch and latch clock are different clock. They are:
Launch Clock:
system_clock_gen_|system_pll_|iopll_0|clkLatch Clock:
SEP_QuadBLKs_Top_|u_AD9633D_SDataProc|LVDS_RX_8Ch6B_inst|lvds_0|core|arch_inst|internal_pll.pll_inst|altera_lvds_core20_iopll|outclk[2]So I thought to add following clock group constain to my project:
set_clock_groups -asynchronous -group {system_clock_gen_|system_pll_|iopll_0|clk} -group {SEP_QuadBLKs_Top_|u_AD9633D_SDataProc|LVDS_RX_8Ch6B_inst|lvds_0|core|arch_inst|internal_pll.pll_inst|altera_lvds_core20_iopll|outclk[2]}However, after compilation, QPP23.4 gave me following warning info:
Ignored filter at my.sdc(21): SEP_QuadBLKs_Top_|u_AD9633D_SDataProc|LVDS_RX_8Ch6B_inst|lvds_0|core|arch_inst|internal_pll.pll_inst|altera_lvds_core20_iopll|outclk[2] could not be matched with a clock Assignment set_clock_groups is accepted but has some problems at my.sdc(21): Argument -group with value SEP_QuadBLKs_Top_|u_AD9633D_SDataProc|LVDS_RX_8Ch6B_inst|lvds_0|core|arch_inst|internal_pll.pll_inst|altera_lvds_core20_iopll|outclk[2] could not match any element of the following types: ( clk )Above warining infos tell me that Quaruts ignored above clock group constrain. Even above info gives the reason why it ignores the constrain. But I still don't know why? Quartus can't identify the LVDS PLL output clock as clock?