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Altera_Forum
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14 years ago

On-Chip Memory in Qsys/Quartus

I have a design based on an Arria II GX part in which Qsys is utilized to generate a system made up of many different interfaces, other components and IP in the design. This system implements a PCIe...
Altera_Forum's avatar
Altera_Forum
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14 years ago

One thing that we discover is that the data that is configured is stored in 3-32 bit words. The data that we are receiving back is information contained in the 3rd byte, spread across 3 addresses.

For example, if I preload in the .hex file data as 0x11223344, 0x55667788, 0x99AABBCC.

The data that is read back from address offsets 0x00 - 0x0C when the read back data type is expected in 32 bit unsigned integer (word) form is:

Address offset Data

0x00 : 0x000000CC

0x04 : 0x000000BB

0x08 : 0x000000AA

0x0C : 0x00000099

When the expected information should be

Address offset Data

0x00 : 0x11223344

0x04 : 0x55667788

0x08 : 0x99AABBCC

Again, I have attempted variations of the configuration of the memory in both Qsys and in Quartus as I established the On Chip RAM component and the .hex file. Is there some way that Quartus is configuring the memory differently than I am expecting? I have also attempted to read other addresses in both directions adjacent to this area without finding any of the 'lost' data.

Here is what was received back from the lscpi command:

01:00.0 Unassigned class [ff00]: Altera Corporation Device e001 (rev 01)

Subsystem: Altera Corporation Device 0004

Physical Slot: 1

Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+

Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-

Latency: 0, Cache Line Size: 64 bytes

Interrupt: pin A routed to IRQ 42

Region 0: Memory at fd000000 (32-bit, non-prefetchable)

Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+

Address: 00000000fee0300c Data: 41a1

Capabilities: [78] Power Management version 3

Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)

Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-

Capabilities: [80] Express (v1) Endpoint, MSI 00

DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us

ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-

DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-

RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+

MaxPayload 128 bytes, MaxReadReq 512 bytes

DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-

LnkCap: Port# 1, Speed 2.5GT/s, Width x4, ASPM L0s, Latency L0 unlimited, L1 unlimited

ClockPM- Surprise- LLActRep- BwNot-

LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-

ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-

LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt-

Capabilities: [100 v1] Virtual Channel

Caps: LPEVC=0 RefClk=100ns PATEntryBits=1

Arb: Fixed+ WRR32- WRR64- WRR128-

Ctrl: ArbSelect=Fixed

Status: InProgress-

VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-

Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-

Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01

Status: NegoPending- InProgress-

Kernel driver in use: PV_PCIE_100461

I hope this helps. I'll check out the tutorial you posted. Thanks.

Steve