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I would raise this as a synth bug to altera, as you will now have a simulation/synthesis missmatch.
Any chance you have a Prime pro license? Prime pro is meant to have full vhdl 2008 support, so I assume a different compile engine.
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You're right, it was such a simple usecase I didn't even bother simulating it (I did test the feature in modelsim a while ago, but this is the first time we're actually using it in project outside just simulation). If you simulate my example above (out <= addr(3 downto 0)) it does behave like I expected it to, but the compilation results are different.
Unfortunately I only have Prime web edition. We do have a license for Quartus 12 but that's so old right now I'm not sure if it's even useful testing it there.
I will raise this bug to Altera as soon as I get back to work on Monday. Thank you for your input!
Honored Contributor
