Open Side Menu
Skip to contentBrand Logo
Forums
BlogKnowledge BaseAltera.com
RegisterSign In
  1. Altera Community
  2. Forums
  3. Quartus® Prime

Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Observing output

Hi, I am a fresh person who have started verilog. I have written a verilog code for an encryption algorithm. Now I want to implement it in an FPGA board. I have a Altera DE1 board and currently us...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

try read article

http://www.google.de/imgres?imgurl=http%3a%2f%2fwww.josepino.com%2farticles%2fdisplay%2f7-segment-lcd-charset.gif&imgrefurl=http%3a%2f%2fwww.josepino.com%2fmicrocontroller%2f7-segment-ascii&h=408&w=455&tbnid=vqkc29wt4r0xym%3a&docid=r0tqt_sugcqplm&ei=6ryuvpcqn8e3swgh9yjqaw&tbm=isch&iact=rc&uact=3&dur=1358&page=1&start=0&ndsp=25&ved=0cc0qrqmwbgovchmi0mkkqyzgyaivx9ssch2hogi6

Recent Discussions

  • Beroual's avatar
    The quartus license works with version 25.0 but not with version 17.0
    1 hour ago
    Beroual
  • Jens's avatar
    Quartus did not start
    6 hours ago
    Jens
  • torerams's avatar
    Docker image for Quartus Pro 26.1 missing ?
    12 hours ago
    torerams
  • cjak's avatar
    Timing analysis - long combinational path
    14 hours ago
    cjak
  • zjj's avatar
    timing violation fix
    20 hours ago
    zjj
Contact Us
Altera YoutubeAltera YoutubeAltera Twitter
  • Company Overview
  • Newsroom
  • Our Leaders
  • Careers
Subscribe to Altera Newsletter

© Altera Corporation | Terms of Use | Privacy Policy | Cookies | Trademarks | PSIRT

Altera Logo