Obscure ModelSim error

Question

I have come across this Modelsim error a few times now: Using the Nativel Link RTL simulation - Quartus 11.1sp1 Web Edition. # ** Fatal: Unexpected signal: 11.
#  ** Error: C:/qdesigns/bv5fpga/bb/ImageDataDispatch/iddRamRead/iddRamRead.vhd(208): VHDL Compiler exiting
#  ** Error: C:/altera/11.1/modelsim_ase/win32aloem/vcom failed. I then usually just switch to Gate Level Timing simulation, but today I have to do a 'long' simulation and I'd like to add RTL signals to the signals pane rather then adding the singular post mapping signals. Any clues here?

altera_forum · Answer

the first line leads me to believe that there's a port/signal/variable that begins with a 11, which i thought Quartus would flat as being illegal VHDL

altera_forum · Answer

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the first line leads me to believe that there's a port/signal/variable that begins with a 11, which i thought Quartus would flat as being illegal VHDL

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If it were that easy I wouldn't have come here!

Anyway I ran Quartus Synthesis first, as you have to before you can start the testbench writer.

altera_forum · Answer

it doesn't hurt to check the obvious  you might try opening ModelSim without invoking it through NativeLink and try compiling the iddRamRead.vhd itself  what's on line 208 of the mentioned file?

altera_forum · Answer

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you might try opening ModelSim without invoking it through NativeLink and try compiling the iddRamRead.vhd itself

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I only recently started using ModelSim in lieu of the internal simulator, the NativeLink is nice as I do all VHDL work inside Quartus. I'll give your suggestion a try.

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what's on line 208 of the mentioned file?

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the final 'end architecture ;'

altera_forum · Answer

I opened ModelSim directly and created a project and add the necessary files. But it chokes on that same file with the same error message. I played around with the options disabling optimizations etc. but to no avail. It obviously is a problem with the ModelSim VHDL compiler that doesn't handle everything the Quartus Synthesiser has no prblem with. Is there a possibility to pipe the output of the Qaurtus Synthesis into Modelsim? Else I guess I'll have to do with the Gate Level Simulation.

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Obscure ModelSim error

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