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Is the In_clk on the board twice as fast as the one you created in simulation?
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Nope. It is produced from a set of master clocks I have set up in my FPGA. This particular clocking signal, when taken to an output pin of the FPGA runs at the correct frequency (and mark to space), i.e. 750KHz.
From the data sheet of this particular IC I am attempting to implement:
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E = Enable pin (I called IN_E). Enables the data-bus input/output buffers and clocks data to & from this device. This signal is usually derived from the system clock.
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I understand what you are saying there about this signal. Wise words. I will rewrite it to common up the clocking event.
BUT! If I hard code the register (the bold code above) to instead to be a the fixed (programmed) value that I expect it to be, i.e:
IF usg_Cntr_HorizAll_7_0 = x"2F" THEN
blah
or
IF usg_Cntr_HorizAll_7_0 = b"00101111" THEN
blah
Still the same! simulates at 64uS, FPGA output pin 32uS.
So, 750KHz = 1.333333uS. 2F = 47: 0..47=48 counts. 48 x 1.3333333uS = 64uS.
Why do I have a
falling edge clocking event you ask:
From the data sheet of IC I am attempting to implement:
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The CLK is an input used to sync all CRT (i.e. this IC) functions except for the processor interface (hence the strange instantiation of IN_E). The active transition is
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So yes, negative edge triggered.
Thank you AGAIN,
Andy
Honored Contributor
