Honored Contributor
Honored ContributorIs the In_clk on the board twice as fast as the one you created in simulation?
on a design note: what is in_e? you are using it as if it were a clock - assuming it is an enable (because it looks like one) this is a bad idea. For a start, assuming in_e is a clock, you are not transfering the reg values into the in_clk domain safely, so you're liable to create meta-stable states on your registers that read the reg values. You should clock all the regs at in_clk (all processes) and then use the in_e as a clock enable:
if falling_edge(in_clk) then
if in_e = '1' then
--do some registering
