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Altera_Forum's avatar
Altera_Forum
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11 years ago

numbers, numbers...

Being new to VHDL, I must admit I find quite confusing the correct application of the use numbers in VHDL. For the problem I wish to have help on in my thread here, I have found that my VHDL si...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

@Tricky, now that is what I call a great post! Wow, you have certainly opened my mind up here. BTW Apologies for delayed response, caught a cold!

I see now why something would simulate and not synthesize. I also wondered how exactly an actual FPGA could support signals which could be in an X, U, - W H or L state. In fact it doesn't - this is only for synthesis.

Understanding that what I assumed were 'numbers' are NOT! They are strings! This to me was the key that unlocked the fundamental understanding of what is going on. As a result, something seemingly innocuous as this: 


  signal count : STD_LOGIC_VECTOR (7 downto 0);
  count <= count + 1;
  if count = b"00000000" then
    blah;

is not as simple as it first appears. I have to stop thinking in terms of code! The '+' is a function! the 1 is an integer! And the comparison is only true if ALL states match 0 and could indeed be Z,X,H,L,- etc. Maybe better to avoid STD_LOGIC_VECTOR and stick to using SIGNED and UNSIGNED where possible. And if adding, maybe design an actual adder if using STD_LOGIC_VECTOR?

I am glad I started this thread. What an eye opener!

Thanks again,

Andy