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Anywho, let me see if I have this right in my tiny brain:
use IEEE.std_logic_1164.all;
defines what various 'standard' states a signal state can be in at any given point in time, i.e. 'Z' 'X' '1' '0' 'W' 'U' 'L' 'H' '-'
A signal (or vector) can be all of these states, or indeed a subset of these. If using a subset, then depending on what is missing (e.g. 'Z') then the simulation may miss out on telling the user that something 'weird' is going on.
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Yes but you got the order wrong, it should be U X 0 1 Z W L H -. this is important as all signals initialise to their leftmost state. And 'U' means "Uninitialised", and might tell you you forgot to set an input in your simulation. Also know that VHDL was origionally written to model digital circuits in the early 80s when such things were all done on PCBs, hence weak high 'H', weak low 'L', weak unknown 'W'. 'Z' means high imedance, which is crucial for tri-state ports (they only exist on the physical pins of the device, any internal tri-states will be converted to muxes in an FPGA). Then finally you have 'X' (unknown) which occurs when you drive two busses together, and '-' (dont care) which is actually quite tricky to use, dispite it's name.
For example, if A = "1111", writing
if A = "10--" then
will only work in simulation when A is exactly "10--", so "1011 will not match (but in synthesis, it would make a circuit that wouldnt care). So in the numeric_std library, there is a std_match function:
if std_match(A, "10--") then
Would work in both simulation and synthesis.
W, L, H do not exist in FPGAs, and neither do X, U and -. Anything assigned to these will be replaced with 0 or 1. Like I said before, Z is only used for tri-states.
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use ieee.numeric_std.all;
(snip)
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You all mostly correct. Not only does it define all those, but it also defines all functions for unsigned and integer types mixed, so
a <= b + 1;
c <= b + x"01";
if x = x"FFFFF1" then
if x = 10 then
Will all work just fine. The functions convert the integer to an unsigned thats the same length as the other unsigned, which is also why you can do:
signal a,b : signed(7 downto 0);
a <= b + "1";
Because it makes both b and "1" into 8 bits before adding them, and because it is signed, it will sign extend the second operand for you (the output here is that a is "11111111").
But be wary - you cannot overload the assignment operator, so you cannot write:
a <= 10;
because a is signed and 10 is an integer. So you need to convert the integer to a signed explicity:
a <= to_signed(10, a'length);
Also note that it can work out the function to call from just the operands, but it will throw a compile error if it finds multiple options for the same function. The classic example is the write function from textio when you're writing a string, as anything in double quotes could be a string or a bit_vector (or a std_logic_vector, unsigned or signed if you're using VHDL 2008), so you need to qualify what you want with the '
write(op, string'("hello world!"));
So, going back to your question about "logic comparision"
if a = "10101010" then
will always know that you meant "10101010" as a signed, as there is no function that exists to compare a signed to unsigned: it already knows that A is signed, so out of the 5 possibilities that "10101010" could be(string, bit_vector, std_logic_vector, signed, unsigned), it knows to pick signed. If you wrote this:
if a = true then
there is no = for signed and boolean, so it throws an error.
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