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Altera_Forum's avatar
Altera_Forum
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11 years ago

numbers, numbers...

Being new to VHDL, I must admit I find quite confusing the correct application of the use numbers in VHDL. For the problem I wish to have help on in my thread here, I have found that my VHDL si...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

It might be easier if you try and explain what you are trying to do.

VHDL has no special number system. I think you're getting confused over the typing system.

An integer in VHDL is just a number. If used in synthesisable code, the synthesisor should convert it into a 32 bit 2's compliment notation.

The numeric_std library defines the unsigned and signed types. unsigned is pure 2^n logic, signed is 2s complement. But the reason we use unsigned is as followed:

1. It gives access to the bits inside the VHDL code.

2. We can set the length ourselves.

(these two also hold true for std_logic_vector also)

3. We can do arithmatic with it.

4. It will roll over - integer type will not (this is useful for things like address generation for FIFOs).

So, I think you're trying to run before you can walk. re-writing the basics that already exist in VHDL show you're trying too much too soon and overcomplicating your learning.