numbers, numbers...

So, not 'good practice' to use a signal logic operators with a clocking event. Gotcha. Do them separately. Roger will-co.

Yes, I have read that std_logic_arith is a non-standard package. Having admitted my guilt over this, as a newbie VHDLer, changing something which at the higher level simulates spot on, is something I was reluctant to do but I will now see if I can change over to using the standard library. I know I will get errors because I am using a MAKE_BINARY function:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.math_real.all;
package CONFIG is
	-- Convert UNSIGNED type to STD_LOGIC_VECTOR type
	function MAKE_BINARY(A : UNSIGNED) return STD_LOGIC_VECTOR;
        ..etc..
end package CONFIG;
package body CONFIG is
    type tbl_type is array (STD_ULOGIC) of STD_ULOGIC;
    constant tbl_BINARY : tbl_type := ('X', 'X', '0', '1', 'X', 'X', '0', '1', 'X');
    function MAKE_BINARY(A : UNSIGNED) return STD_LOGIC_VECTOR is
	variable one_bit : STD_ULOGIC;
	variable result : STD_LOGIC_VECTOR (A'range);
    begin
	    for i in A'range loop
		  result(i) := tbl_BINARY(A(i));
	    end loop;
	    return result;
    end;
end CONFIG;

Yes, I copied that lot (not my own, hell I'm learning VHDL ;) ). No doubt more non-standard horribleness.

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If the hard coded value gives a different result to the register version, I can only assume the CPU is writing the wrong number.

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Maybe. But the signals are (as far as I can tell) that come from my core processor when first programming this VHDL model of my 'chip' are spot on as well. The simulator couldn't 'see' these actual register contents, so I might now simply add a vector such that I can monitor the register contents.

Thanks again!

Andy