numbers, numbers...

You cannot use two clock events in the same process - how do you expect this to work? the two clocks would have to be exactly co-incident for it to even work conceptually, but there is no way it will work on real hardware.

But mtushi is correct in saying using gated clocks is a bad idea. So do not use in_e as a clock - use the in_clk as the clock and in_e as enable:

elsif falling_edge (IN_CLK) then 
       if IN_E = '1' and IN_CSn='0' and IN_RW='0' then    --Grab data from data bus and program into indexed register.

And yes, also stop using std_logic_arith. It is not a standard VHDL package, numeric_std is.

If the hard coded value gives a different result to the register version, I can only assume the CPU is writing the wrong number.