numbers, numbers...

Hi,

First you made a pseudo gated clock with a different "clock"which is bad. I suggest you to resynchronize with your system clock (IN_CLK).

Even if it makes sense in VHDL, It is smarter using a whole unique system clock (IN_CLK) in this case.

You can correct this with :

ext_write : process(IN_RESETn, IN_CLK)
begin                           
  if IN_RESETn = '0' then        
    REG_R00_HORIZ_TOTAL_7_0  <= b"0010_1111";
  elsif falling_edge (IN_CLK) then 
       if falling_edge(IN_E) and IN_CSn='0' and IN_RW='0' then    --Grab data from data bus and program into indexed register.
          case REG_INDEX_ADDR_4_0 is                                         --Use Reg Index to write D0-7 to reg
              when INDEX_HT => REG_R00_HORIZ_TOTAL_7_0 <= IO_D_7_0;
etc

Secondly,

LIBRARY ieee;
USE ieee.STD_LOGIC_1164.all; -- 'Z' 'X' '1' '0' 'W' 'U' 'L' 'H' '-'
USE ieee.numeric_std.all; -- UNSIGNED, SIGNED,  + - * / mod