now able to simulate altpll using vwf file

hi,

i am new to this, and trying to simulate altpll with input clock frequency of 27Mhz, however, when i set that input clock of 37037 ps, i am not able to lock it, below is my altpll setting, did i do anything wrong? it seem to be working fine when i program it into the altera Cyclone II DEII board. i have attached my vwf output, can someone help me on this.. thanks

i am seeing below warning during compilation

Info: System task: Warning : Input clock freq. is not within VCO range. PLL may not lock

below is the module

   module VGA_Audio_PLL (
    areset,
    inclk0,
    c0,
    c1,
    c2);
    input      areset;
    input      inclk0;
    output      c0;
    output      c1;
    output      c2;
    wire  sub_wire0;
    wire  sub_wire6 = 1'h0;
    wire  sub_wire3 = sub_wire0;
    wire  sub_wire2 = sub_wire0;
    wire  sub_wire1 = sub_wire0;
    wire  c0 = sub_wire1;
    wire  c1 = sub_wire2;
    wire  c2 = sub_wire3;
    wire  sub_wire4 = inclk0;
    wire  sub_wire5 = {sub_wire6, sub_wire4};
    altpll    altpll_component (
                .inclk (sub_wire5),
                .areset (areset),
                .clk (sub_wire0),
                .activeclock (),
                .clkbad (),
                .clkena ({6{1'b1}}),
                .clkloss (),
                .clkswitch (1'b0),
                .configupdate (1'b0),
                .enable0 (),
                .enable1 (),
                .extclk (),
                .extclkena ({4{1'b1}}),
                .fbin (1'b1),
                .fbmimicbidir (),
                .fbout (),
                .locked (),
                .pfdena (1'b1),
                .phasecounterselect ({4{1'b1}}),
                .phasedone (),
                .phasestep (1'b1),
                .phaseupdown (1'b1),
                .pllena (1'b1),
                .scanaclr (1'b0),
                .scanclk (1'b0),
                .scanclkena (1'b1),
                .scandata (1'b0),
                .scandataout (),
                .scandone (),
                .scanread (1'b0),
                .scanwrite (1'b0),
                .sclkout0 (),
                .sclkout1 (),
                .vcooverrange (),
                .vcounderrange ());
    defparam
        altpll_component.clk0_divide_by = 15,
        altpll_component.clk0_duty_cycle = 50,
        altpll_component.clk0_multiply_by = 14,
        altpll_component.clk0_phase_shift = "0",
        altpll_component.clk1_divide_by = 3,
        altpll_component.clk1_duty_cycle = 50,
        altpll_component.clk1_multiply_by = 2,
        altpll_component.clk1_phase_shift = "0",
        altpll_component.clk2_divide_by = 15,
        altpll_component.clk2_duty_cycle = 50,
        altpll_component.clk2_multiply_by = 14,
        altpll_component.clk2_phase_shift = "-9921",
        altpll_component.compensate_clock = "CLK0",
        altpll_component.inclk0_input_frequency = 37037,
        altpll_component.intended_device_family = "Cyclone II",
        altpll_component.lpm_type = "altpll",
        altpll_component.operation_mode = "NORMAL",
//