Hi all, I have a problem with generating a random from the uniform function, it is always the same with each execution of the process. I have attached a piece of code to the testbench. If someone gets to see where it's wrong. Thank you

Looks fine from the small low res picture, but I cannot see the whole file. Why do you assign int_rand back to itself? Why not post the code so we can try it

Thank you for ur reply, here is my code, it should be enough to test it --- Quote Start --- --main process p_main: process (clk, rst_n) variable seed1, seed2 : positive; variable rand : real; variable int_rand : integer range 0 to 1000; variable counter, count_hash, num_test: integer; variable line_in, line_out : line; variable temp: std_logic_vector(63 downto 0); file filein : text open read_mode is "c:\users\simo\Desktop\Keccak_core\new_test_vector/keccak_in.txt"; file fileout : text open write_mode is "c:\users\simo\Desktop\Keccak_core\new_test_vector/keccak_out_compact_vhdl.txt"; begin if rst_n = '0' then -- asynchronous rst_n (active low) st <= initial; counter:=0; din<=(others=>'0'); count_hash:=0; init<='0'; absorb<='0'; squeeze<='0'; go<='0'; rand_num <= 1; elsif clk'event and clk = '1' then -- rising clk edge uniform (seed1, seed2, rand); int_rand := INTEGER(TRUNC(rand*1000.0)); int_rand := int_rand; report "random is :" & integer'image(int_rand) severity NOTE; --is not random at each execution --- Quote End ---

I assign int_rand back to itself by mistake, we can even comment it if we want

Your code (once I removed all the illegal signal assignments) works fine: # ** Note: random is :999 # Time: 40 ns Iteration: 0 Instance: /tester # ** Note: random is :974 # Time: 50 ns Iteration: 0 Instance: /tester # ** Note: random is :647 # Time: 60 ns Iteration: 0 Instance: /tester # ** Note: random is :333 # Time: 70 ns Iteration: 0 Instance: /tester # ** Note: random is :36 # Time: 80 ns Iteration: 0 Instance: /tester # ** Note: random is :161 # Time: 90 ns Iteration: 0 Instance: /tester # ** Note: random is :664 # Time: 100 ns Iteration: 0 Instance: /tester # ** Note: random is :84 # Time: 110 ns Iteration: 0 Instance: /tester # ** Note: random is :204 # Time: 120 ns Iteration: 0 Instance: /tester # ** Note: random is :167 # Time: 130 ns Iteration: 0 Instance: /tester # ** Note: random is :654 # Time: 140 ns Iteration: 0 Instance: /tester # ** Note: random is :128 # Time: 150 ns Iteration: 0 Instance: /tester # ** Note: random is :910 # Time: 160 ns Iteration: 0 Instance: /tester # ** Note: random is :111 # Time: 170 ns Iteration: 0 Instance: /tester # ** Note: random is :299 # Time: 180 ns Iteration: 0 Instance: /tester # ** Note: random is :265 # Time: 190 ns Iteration: 0 Instance: /tester # ** Note: random is :699 # Time: 200 ns Iteration: 0 Instance: /tester

yes you are rghit it gives that, but If you run it another time it will give u the same numbers so it's not random in my opinion !

not random at each execution | Altera Community

16 Replies

Altera_Forum
Honored Contributor
9 years ago
For testing, you NEED re-createable results, so having it fully random would be of a hinderance rather than a help.
On hardware, you cannot even use the uniform function, so you will need some form of random number generator. You could use an LFSR, but it works similarly, in that once you give it a seed you'll get the same sequence.
Altera_Forum
Honored Contributor
9 years ago
--- Quote Start ---
For testing, you NEED re-createable results, so having it fully random would be of a hinderance rather than a help.
On hardware, you cannot even use the uniform function, so you will need some form of random number generator. You could use an LFSR, but it works similarly, in that once you give it a seed you'll get the same sequence.
--- Quote End ---

Okay. I'll try a pseudo RNG that i have .
It is clear I will be able to change his seed. After I will try to see how to make it change with each simulation launch.
Altera_Forum
Honored Contributor
9 years ago
--- Quote Start ---
Okay. I'll try a pseudo RNG that i have .
It is clear I will be able to change his seed. After I will try to see how to make it change with each simulation launch.
--- Quote End ---

The best way to do it is to have a generic that assigns the seed, then you can assign this when you launch the simulation.
Altera_Forum
Honored Contributor
9 years ago
[h=3]Okay, Good idea.

Another question that I am asking, if I can have the effect random but Synthesizable on FPGA ?

thank you
[/h]
Altera_Forum
Honored Contributor
9 years ago
--- Quote Start ---
[h=3]Okay, Good idea.

Another question that I am asking, if I can have the effect random but Synthesizable on FPGA ?

thank you
[/h]
--- Quote End ---

uniform is not a synthesisable function, as real types are not synthesisable
You will need to build a LFSR, which generates a pseudo random sequence, otherwise you'll have to investigate other methods of generating random numbers in FPGA.
Altera_Forum
Honored Contributor
9 years ago
Okay, i will try to integrate the LFSR into my system. thank for the proposition.
see you soon

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not random at each execution

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