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Pooja_03's avatar
Pooja_03
Icon for New Contributor rankNew Contributor
1 year ago

Not able to get the 3.3V peak to peak from PLL generated output signal

Hi, I have generated a PLL (ALTPLL) IP in Quartus Lite software for the MAX10 FPGA (10M50DAF484C6GES). In the IP configuration, I set the input frequency to 50 MHz and generated an output frequency ...
Hdl
Pooja_03's avatar
Pooja_03
Icon for New Contributor rankNew Contributor
1 year ago

Hi,

We are using MAX10 (10M50DAF484C6GES) Deca Board for testing the output frequency from GPIO (pin V17, W18, Y6, W6).

Scope details : - Tektronix MDO3024 Mixed domain oscilloscope (scope is fine because we have tested other designs as well).

we tried with different probe as well issue remains the same.

Please help us to understand where is the issue.

PFA image for your reference.

Thank you

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 year ago
    Hi,
    the waveform looks as expected, due to bandwidth limiting, the square wave is displayed as sine with reduced magnitude.
    As far as I know, MDO3024 has 200 MHz channel bandwidth, correct me if I'm wrong. To reproduce a 100 MHz square wave, you need 500 MHz - 1 GHz bandwidth. Another possible issue can be capacitive pin loading by oscilloscope probe and low IO drive strength.
    Realistically, you most likely don't have the measurement tools to visualize 100 or even 250 MHz FPGA output signal.