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Altera_Forum's avatar
Altera_Forum
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13 years ago

Nonresolved signal has multiple sources

Hi all, A homework task I got is to create a component which receives positive numbers and gives the output of A+B-C+D-E...

Compiling the code yields one error:

# ** Error: checkex4.vhd(103): Nonresolved signal 'cur_RES' has multiple sources. The signal "cur_RES" is the output of the FF whom is responsible for the memory for the next cycle. I don't see why there is a problem with the code. (I can guess it's connected to the clock and sync options ?)

The sketch which I have done for the component is:

https://www.alteraforum.com/forum/attachment.php?attachmentid=7227

(The code is attached to the question)

Thanks in advance, Amitai

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    cur_reset is assigned 0 after begin then it is driven again by a component. So are some other signals. This is multiple drive and need to be resolved by user.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    The program still doesn't work as expected and the output

    has for some reason different clock time then the rest of the

    circuit, any idea why?

    Thanks, Amitai
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    According to your diagram, the right code is (without the double register) 

    if rising_edge(clk) then
  if Rst_n='0' then
    cs <= '0';
    cr <= 0;
  else	
    cs <= ns;
    cr <= cr + muxo;
    --cr <= nr;
  end if;
end if;

    To improve readability I would pull everything into the process. 

             
if rising_edge(clk) then
  if Rst_n='0' then
    cs <= '0';
    cr <= 0;
  else	
    cs <= not cs;
    if cs = '0' then   
      cr <= cr + D_in;
    else   
      cr <= cr - D_in;
    end if;   
  end if;
end if;

    P.S.: Different from your code, the diagram seems to suggest an asynchronous reset.