library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all; 

entity taylor_seq is 
  port (D_in  : in  integer;
        Rst_n : in  std_logic;
        clk   : in  std_logic;
        RES   : out integer );       
end entity;

architecture arc_taylor_se of taylor_seq is
   
  signal din,dneg,muxo,nr : integer; 
  signal cr :integer := 0;
  signal ns	: std_logic;
  signal cs : std_logic := '0';
    
  begin  
    din   <=  D_in;
    dneg  <= -D_in;
    
    muxo <= din when cs='0' else dneg;
    ns <= not cs;

    toggle_sign : process (clk) 
    begin
        if rising_edge(clk) then
            if Rst_n='0' then
				cs <= '0';
				cr <= 0;
			else	
				cs <= ns;
				nr <= cr + muxo;
  			    cr <= nr;
			end if;
		end if;	
	 	RES <= cr;
	end process;

end architecture;