Node * determined to be a clock

--- Quote Start ---

challenge_out is wired to challenge_dr and is viewed as same node for clocking purpose. So check that challenge_out is used as clock

--- Quote End ---

You are right! challenge_out goes as select into the MUX. The MUX selects the outputs of different ring oscillators whose edges are counted by a counter. (See the attached image for explanation of Ring-Oscillator Physically Unclonable Functions.) The counter's input is indeed defined as clock:

entity counter is
    port (
            -- Input ports
            clk                : in std_logic;
            reset             : in std_logic;
            start_counter    : in std_logic;
            stop_counter    : in std_logic;
            
            -- Output ports
            count : out std_logic_vector(127 downto 0)
        );
end entity counter;
    
architecture logic of counter is
    signal tmp_count        : std_logic_vector(127 downto 0) := (others => '0');
    signal run_counter    : std_logic := '0';
    
begin
        
        process(clk,reset)
        begin
            if reset = '1' then
                tmp_count <= (others => '0');
            elsif rising_edge(clk) then
                if run_counter='1' then
                    tmp_count <= tmp_count + 1;
                end if;
            end if;
        end process;
        
        process(start_counter,stop_counter)
        begin
            if start_counter='1' then
                run_counter<='1';
            elsif stop_counter='1' then
                run_counter<='0';
            end if;
        end process;
        
        count <= tmp_count;
        
end architecture logic;

So should I ignore the warning or is there a way to suppress it via more explicit code?

Thanks,

Linus