Node * determined to be a clock

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Hello,

I seem to have a similar problem, being rather unexperienced with Quartus. I too get the warning:

Warning (332060): Node: ... was determined to be a clock but was found without an associated clock assignment.

I am writing a controller to process the inputs from the MegaWizard Virtual JTAG node (passed from a PC to the FPGA with the tcl-command "device_virtual_dr_shift"). The value I am interested in is called "challenge". I need to shift it into the controller bit by bit but at the same time I want it to be available at an output of the controller.

Here is the relevant part of my code:

entity controller is
   generic
   (
      challenge_width   : integer := 8
   );
   port
   (
      ir_in           : in std_logic_vector(7 downto 0);
      tck_in         : in std_logic;
      tdi_in         : in std_logic;
      shift_dr_in      : in std_logic;
      challenge_out      : out std_logic_vector((challenge_width-1) downto 0);
   );
end controller;
architecture arch of controller is
   -- Instruction codes.
   constant C_PUSH_CHALLENGE   : std_logic_vector(7 downto 0) := "00000001";
   
   -- Register.
   signal challenge_dr   : std_logic_vector((challenge_width-1) downto 0);
begin
   challenge_out <= challenge_dr;
   process(tck_in)
   begin
      if rising_edge(tck_in) then
         if ir_in = C_PUSH_CHALLENGE and shift_dr_in = '1' then
            challenge_dr <= tdi_in & challenge_dr((challenge_width-1) downto 1);
         end if;
      end if;
   end process;
end arch;

As I said above, challenge_dr is causing the warnings:

Warning (332060): Node: controller:control|challenge_dr[0] was determined to be a clock but was found without an associated clock assignment.

Warning (332060): Node: controller:control|challenge_dr[4] was determined to be a clock but was found without an associated clock assignment.

Any ideas how to handle this?

Thanks,

Linus

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your problem isn't in the piece of code given above. challenge_dr must have been used somewhere else as clock.