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Altera_Forum
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11 years ago

No PLL output on modelsim

Hi all,

I am using quartus 2 9.1 sp2. I want to run an ALTPLL considering only one input (Clk) and two output ( c0 and locked output). I have generated the vhdl file for modelsim. I simulate it with 50MHz clock and i see no output on both the output signals. Please see the files below for .bdf and modelsim screenshot. Please help me how to see the output and what changes i need to make.

Thank you

Ash

24 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi Ash,

    Just to check with you if the pll_locked got asserted? Can you try to apply a reset to the PLL?
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    yea that's what i have designed in Mega wizard plug in manager. I have chosen 50MHz for the input clock

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi akira,

    yea that's what i have designed in Mega wizard plug in manager. I have chosen 50MHz for the input clock

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi tiny007,

    I added a reset as per what you said. still the output remains the same Undefined. Is there somewhere i am going wrong?
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi amod,

    Two things: you only show 5-6 ns on your waveforms, the PLL models, like real PLLs, take some time to initialize and sync before you get an output. 6ns is not nearly enough time. I forget how long this takes in simulation (I think it's a lot less than for the real devices) but give it a us or so before you give up. Second, it looks like the clock you're feeding it is NOT 50MHz, but 10GHz! The period shown is 0.1ns, check your clock generation.

    -Fred
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi FredH i have changed the clock period to 0.02 us and run the simulation for half a second. still my output remains the same. Please see the attachment.

    Thanks

    Ash
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi krasner,

    Could you please explain me how to generate testbench ?