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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

No paths found for timing analysis

When I compile the following code, the compilation proceeds successfully, but the classic timing analyser of quartus generates the warning "Warning: No paths found for timing analysis". The RTL viewer shows that the output is connected to the inputs accordingly to the expression in the process clause. Could somebody tell me what is wrong with timing analysis?

LIBRARY IEEE;

LIBRARY LPM;

USE IEEE.STD_LOGIC_1164.ALL;

USE LPM.LPM_COMPONENTS.ALL;

USE IEEE.NUMERIC_STD.ALL;

ENTITY Component_test_wo_library IS

GENERIC

(

mod_0_unsigned_width_n : NATURAL := 8;

mod_0_unsigned_width_d : NATURAL := 8;

mult_0_unsigned_width_a : NATURAL := 3;

mult_0_unsigned_width_b : NATURAL := 5;

add_0_unsigned_width : NATURAL := 8;

sub_0_unsigned_width : NATURAL := 5;

div_0_unsigned_width_n : NATURAL := 9;

div_0_unsigned_width_d : NATURAL := 5

);

PORT

(

--Input ports

Input1_I : IN STD_LOGIC_VECTOR(mult_0_unsigned_width_a-1 DOWNTO 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,mult_0_unsigned_width_a));

Input2_I : IN STD_LOGIC_VECTOR(mult_0_unsigned_width_b-1 DOWNTO 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,mult_0_unsigned_width_b));

Input3_I : IN STD_LOGIC_VECTOR(sub_0_unsigned_width-1 DOWNTO 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,sub_0_unsigned_width));

Input4_I : IN STD_LOGIC_VECTOR(mod_0_unsigned_width_n-1 DOWNTO 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,mod_0_unsigned_width_n));

Input5_I : IN STD_LOGIC_VECTOR(mod_0_unsigned_width_d-1 DOWNTO 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(1,mod_0_unsigned_width_d));

Input6_I : IN STD_LOGIC_VECTOR(sub_0_unsigned_width-1 DOWNTO 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(1,sub_0_unsigned_width));

--Output ports

Result_O : OUT STD_LOGIC_VECTOR(div_0_unsigned_width_n-1 DOWNTO 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(0,div_0_unsigned_width_n))

);

END Component_test_wo_library ;

ARCHITECTURE a OF Component_test_wo_library IS

SIGNAL Read_Write : STD_LOGIC := '0';

BEGIN

Component_test_wo_library:

PROCESS (Input1_I,Input2_I,Input3_I,Input4_I,Input5_I,Input6_I,Read_Write) IS

BEGIN

Read:

IF (Read_Write = '0')

THEN

Read_Write <= '1';

END IF;

Result:

IF (Read_Write = '1')

THEN

Read_Write <= '0';

Result_O <= std_logic_vector( (("0" & unsigned(Input1_I) * unsigned(Input2_I)) + (unsigned(Input4_I) mod unsigned(Input5_I))) /

(unsigned(Input6_I) - unsigned(Input3_I)) );

END IF;

END PROCESS;

END a;

13 Replies

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I have conducted a few more experiments just to be sure that the problem is in the tool. Indeed, the tool calculates a worst-case tpd following some formula that takes tpd of every operation involved in calculations, e.g., tpd=(n-1)*(tpd,or+tpd,and) or the like.

    For instance, if I try the following code:

    PROCESS (Input_I,Read_Write) IS

    BEGIN

    Read:

    IF (Read_Write = '0')

    THEN

    Read_Write <= '1';

    END IF;

    Result:

    IF (Read_Write = '1')

    THEN

    Read_Write <= '0';

    Result1_O <= not Input_I;

    END IF;

    the tool cannot process it because there is no information about tpd of bitwise not operation in a process. Since the subtraction operation is performed as an addition of two's complement (a-b=a+not(b)), the tool cannot calculate tpd for this expression. Furthermore, it does not depend on a device family as I have tried different ones and have got the same result. However, the tool works fine for other operations logical, arithmetical etc.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    To check your assumptions about the cause of timing analysis failure, please compile the below modified code. You'll notice that timing analysis works as soon as the latch is controlled by a signal of known timing. 

    LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY no_timing IS
PORT (
  Read_Write2 : STD_LOGIC;
  --Input ports
  Input_I : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
  --Output ports
  Result_O : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END;
ARCHITECTURE a OF no_timing IS
SIGNAL Read_Write : STD_LOGIC := '0';
BEGIN
  PROCESS (Input_I,Read_Write) IS 
    BEGIN
      IF (Read_Write = '0') THEN 
        Read_Write <= '1';
      END IF;
      --IF (Read_Write = '1')
      IF (Read_Write2 = '1') THEN 
        Read_Write <= '0';
        Result_O <= not Input_I;
      END IF;
  END PROCESS;
END;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    You'll notice that timing analysis works as soon as the latch is controlled by a signal of known timing.

    --- Quote End ---

    Yes, I agree with you and the example you have proposed works. Somehow, the tool can calculate timing for every operation but the "not" one unless the timing is controlled explicitly.