No paths found for timing analysis

To check your assumptions about the cause of timing analysis failure, please compile the below modified code. You'll notice that timing analysis works as soon as the latch is controlled by a signal of known timing.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY no_timing IS
PORT (
  Read_Write2 : STD_LOGIC;
  --Input ports
  Input_I : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
  --Output ports
  Result_O : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END;
ARCHITECTURE a OF no_timing IS
SIGNAL Read_Write : STD_LOGIC := '0';
BEGIN
  PROCESS (Input_I,Read_Write) IS 
    BEGIN
      IF (Read_Write = '0') THEN 
        Read_Write <= '1';
      END IF;
      --IF (Read_Write = '1')
      IF (Read_Write2 = '1') THEN 
        Read_Write <= '0';
        Result_O <= not Input_I;
      END IF;
  END PROCESS;
END;